The present invention relates to a method for designing the layout of a semiconductor device, and particularly, to a method for designing the layout of a standard cell semiconductor device.
FIG. 1 is a schematic diagram showing the layout of a prior art standard cell semiconductor device 1. The semiconductor device 1 includes a plurality of cell rows 2. To lay out logic cells A, which are provided with logic functions, the logic cells A are first arranged in each cell row 2. Then, spacer cells B are arranged in vacant areas that are not occupied by the logic cells A (vacant areas) to connect the logic cells A to a power source (not shown). The spacer cells B each includes dimension data and power line data. The spacer cells B are arranged to correspond with the dimensions of the vacant areas to connect the power lines of the logic cells A.
In recent years the scale of semiconductor device 1 has been increasing. This has resulted in the arrangement having auxiliary functions on the semiconductor device 1. Auxiliary cells may include, for example, a master slice basic cell for making logic changes or for adjusting timing with metal modification, an antenna effect diode cell for preventing characteristic deterioration during the fabrication process, and capacitance cells for preventing power supply noise.
The size of each vacant area is determined by the layout of the logic cells A. Each type of auxiliary cells has a different size. Thus, it is difficult to arrange auxiliary cells of different dimensions, and the designing of the semiconductor device 1 may be time consuming.